1. Field of the Invention
Embodiments of the present invention relate generally to semiconductor device assemblies that include more than one semiconductor die. More specifically, embodiments of the present invention relate generally to semiconductor device assemblies that include electrically conductive paths that provide electrical communication between semiconductor dice in such semiconductor device assemblies and conductive structures of a substrate to which the semiconductor dice are structurally and electrically coupled. Embodiments of the present invention further relate to semiconductor device assemblies, to methods of fabricating such semiconductor device assemblies and to systems that include such semiconductor device assemblies.
2. Background of Related Art
In order to conserve the amount of surface area, or “real estate,” consumed on a carrier substrate, such as a circuit board, by semiconductor devices coupled thereto, various types of increased circuit density semiconductor devices have been developed. Some types of semiconductor device assemblies include semiconductor dice or semiconductor device packages that are stacked one over another. Among these various types of semiconductor devices are stacked multi-chip modules (MCMs) and package-on-package (POP) assemblies. The amount of surface area on a carrier substrate that may be saved by stacking semiconductor dice or semiconductor device packages is readily apparent. A stack of semiconductor dice or semiconductor device packages may consume roughly as little real estate on a carrier substrate as a single, horizontally oriented semiconductor die or semiconductor device package.
Another benefit of stacked semiconductor device assemblies is flexibility in manufacturing, as they provide a variety of configurations, while enabling high-volume semiconductor device production. By way of example and not limitation, stacked semiconductor device assemblies may be manufactured that combine various numbers of like semiconductor devices, such as dynamic random-access memory (DRAM) devices, providing a memory module that may be configured to a selected storage capacity. Stacked semiconductor device assemblies may also be manufactured that combine various numbers of different semiconductor devices. For example, a semiconductor device assembly may include a DRAM device, a non-volatile Flash memory device, and an application specific integrated circuit (ASIC) device, thereby combining the functionality of each semiconductor device into a single module. This is advantageous, as one may use a relatively small variety of semiconductor devices, which may be combined in a diversity of ways, and create a large variety of stacked semiconductor device assemblies with differing functionalities.
Semiconductor device assemblies typically include electrically conductive paths that provide electrical communication between the dice and a substrate to which dice are, or may be, attached. The electrically conductive paths are conventionally formed on or within a substrate, which provides them with support and mutual electrical isolation. Various designs of semiconductor device assemblies including such conductive paths have been disclosed in the art.
U.S. Pat. No. 5,977,640, to Bertin et al., which issued Nov. 2, 1999, discloses a stacked multi-chip module, including a chip-on-chip (COC) component, where the active region of a first chip is electrically coupled to the active region of a second chip. The COC component is coupled to a substrate, the upper surface of the substrate having solderable metallurgical pads and the lower surface having solder balls. Multiple components can then be stacked and coupled, with the solder balls on the bottom surface of a component corresponding to the metallurgical pads on the top surface of another component.
U.S. Pat. No. 6,020,629, to Farnworth et al., which issued Feb. 1, 2000 and is assigned to the assignee of the present invention, discloses a stacked multi-chip module, including multiple substrates, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate. Interlevel conductors through the substrate interconnect the external contacts and contact pads. The external contact pads on a substrate are bonded to the contact pads on an adjacent substrate, such that all of the dice in the package are interconnected.
U.S. Pat. No. 6,072,233, to Corisis et al., which issued Jun. 6, 2000 and is assigned to the assignee of the present invention, discloses a package-on-package assembly in which fine ball grid array (FBGA) packages are stacked one upon another. Each FBGA package is configured such that conductive elements on the package extend beyond one or more of the major surfaces and make contact with adjacent FBGA packages in the stack.
U.S. Pat. No. 6,225,688, to Kim et al., which issued May 1, 2001, discloses a stacked multi-chip module, which includes a flexible substrate having a wiring layer with conductive paths extending to a plurality of attachment sites. A plurality of microelectronic components is assembled to the attachment sites, and the flexible substrate is folded so as to provide a stacked assembly with conductive terminals exposed at the bottom end of the stack.
U.S. Pat. No. 6,323,060, to Isaak, which issued Nov. 27, 2001, discloses a stacked multi-chip module, including multiple flex circuit integrated circuit (IC) packages. The patent teaches a flex circuit, which is comprised of a flexible base with a conductive pattern disposed thereon, that is wrapped around a frame, having an IC device mounted there within. The conductive pattern of the flex circuit is electrically coupled to the IC device, forming a stackable flex circuit IC package. Multiple flex circuit IC packages can then be stacked and electrically coupled using a conductive epoxy.